Senior Hardware Design Engineer (Low Latency) in City of London
New Yesterday
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Job Description
Overview:
My client is a global tech firm seeking an FPGA/ASIC Hardware Engineer to design high-performance, low-latency compute systems.
You’ll design RTL in SystemVerilog, optimise data pipelines, and work on advanced hardware platforms in a hands-on, performance-focused role—no industry background required.
Key responsibilities:
Design and develop FPGA and/or ASIC solutions as part of a cross-functional engineering team
Implement and optimise RTL for complex data structures and processing pipelines
Explore and evaluate new tools, technologies, and architectures
Contribute to a fast-moving, modern hardware development environment
Key requirements:
4+ years’ experience in FPGA or ASIC RTL design
Strong SystemVerilog expertise
Deep understanding of FPGA/ASIC architectures and low-level hardware behaviour
Experience with networking, data pipelines, or hardware acceleration (ML a plus)
Working knowledge of Python and/or C++
Comfortable in a Linux environment with strong verification skills
Degree in Electrical Engineering, Computer Science, or related field
If you are interested in applying for this job please press the Apply Button and follow the application process. Energy Jobline wishes you the very best of luck in your next career move.
- Location:
- City Of London
- Job Type:
- FullTime
